1. Field of the Invention
The present invention relates to a stackable semiconductor chip, stacked semiconductor chip package and fabrication methods thereof.
2. Description of the Conventional Art
Generally, the three-dimensional chip stacking technique is a key technique for developing a high capacity and small-sized semiconductor chip package. This technique is disclosed in U.S. Pat. No. 5,104,820 and U.S. Pat. No. 5,279,991.
FIG. 1 illustrates a portion of the three-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,104,820. As shown, a wafer 2 is divided into a plurality of semiconductor chips 11 by separation lines 4. The pads 12 for one of the semiconductor chips 11 is also shown. A conductive wire 13 is connected to each one of the pads 12, and terminates in a realigned pad 14. In this manner, the pads 12 are realigned. Unfortunately, realigning the pads 12 requires forming conductive wires 13 over adjacent semiconductor chips 11, rendering those chips unusable. Thus, the yield for the wafer 2 is also significantly reduced.
Next, the semiconductor chips 11 are cut along the separation lines 4. The semiconductor chips 11 with conductive wires 13 formed thereon, however, are not separated from the semiconductor chip 11 having the pads 12; the conductive wires 13 being connected to the pads 12. The thusly separated chips 11 are stacked and formed into a module. Then, the side surfaces of each chip 11 in a module are insulated from the sides of the other chips 11.
The insulation of the sides of each chip will now be explained in more detail. In the module in which padre-aligned chips are stacked in multiple layers, the side surfaces of each chip are etched except for end portions of the conductive wires 13, and a polymer insulation is filled in the etched portions; thus insulating the side surfaces of each chip. Namely, the side surface insulation process is not performed in the wafer state but is performed on the stacked chip module.
The disadvantages of the conventional three-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,104,820 will now be explained. First, since many processes are performed on each stacked chip module, it is impossible to adapt conventional wafer processing techniques thereto. Second, the yield of the wafer, as discussed above, is significantly reduced (about six-fold).
Third, in order to insulate the laterally realigned pads, additional process step such as chip etching and insulation polymer coating are needed; thus increasing the fabrication cost of the semiconductor chip.
In the three-dimensional chip stacking technique disclosed in U.S. Pat. No. 5,279,991, the chips with laterally realigned pads are all stacked to form a bigger unit than a module of chips, and then the lateral surfaces of each chip are insulated. This big stacked chip unit is separated into stacked chip modules. Again, this technique requires performing many processes on the big stacked chip unit. It is impossible to directly adapt conventional wafer processing techniques thereto, thus complicating processing. In addition, an increased number of equipment must be used due to the complicated processing.